AI Chips: what are the biggest challenges now?
In our AI chip market deck, you will find everything you need to understand the market
SUMMARY
AI chips are being constrained most by HBM, power and cooling, networking, advanced packaging, software, and a highly concentrated supply chain. Raw accelerator performance is still improving extremely fast; the harder job now is turning those accelerators into complete, deployable AI systems.
The sharpest manufacturing constraint has moved toward memory. Nvidia, Google, AMD and Amazon were already consuming roughly 90% of global HBM supply in 2025, while their share of advanced 3–5 nm logic production was only about 12%.
Advanced packaging is still tight, but the direction is different. TSMC expanded CoWoS capacity enough to create some headroom, while HBM consumption kept climbing toward almost the entire global supply available to the largest US accelerator designers.
Compute scarcity increasingly means deployment scarcity. A GPU only becomes useful once it has memory, packaging, switches, network links, rack space, electrical capacity and cooling around it, so a shortage at any one of those layers can strand very expensive silicon.
Power is becoming one of the slowest-moving parts of the AI stack. Semiconductor generations can change in a year or two, while substations, transmission upgrades and utility connections often take much longer, creating a timing problem that better chips cannot solve by themselves.
Networking is moving closer to the center of chip competition. The more accelerators a training or inference cluster contains, the more performance depends on keeping thousands of devices fed with data and synchronized rather than simply maximizing peak FLOPS.
Nvidia's advantage now extends well beyond CUDA. Its position combines software, networking, rack-scale architecture and a mature deployment ecosystem, which is why a technically competitive accelerator can still be an expensive replacement for customers to adopt.
Custom chips will keep taking workloads from general-purpose GPUs, especially inside hyperscalers. But the largest buyers are already showing that custom silicon and Nvidia GPUs can grow at the same time because flexibility still matters when model architectures and inference patterns keep changing.
AI-chip economics increasingly turn on utilization and cost per useful output. Hardware that looks cheaper or faster on a spec sheet can lose badly if memory limits, networking, software friction or poor scheduling leave too much of the system idle.
The overall pattern is that AI chips have become a systems-engineering race. HBM currently deserves the top spot among manufacturing bottlenecks, while power, networking, packaging, software and supply-chain concentration determine how much of each new accelerator generation can actually be converted into useful compute.
This market map, featured in our AI chip market deck, highlights top companies and startups in the AI chip market
What is actually slowing AI chips down today?
The biggest AI-chip problem today is getting enough memory, packaging, networking, electricity and cooling around the accelerators we already know how to build.
That is a fairly big change from the way this market was discussed a few years ago. Back then, the obvious question was whether Nvidia, AMD or another designer could keep making the processor itself faster. These days, the accelerator is only one part of a much bigger machine.
Epoch AI reconstructed the supply chain for Nvidia, Google, AMD and Amazon and found that those four designers consumed around 90% of global HBM and CoWoS-class advanced-packaging capacity in 2025, against only about 12% of advanced 3–5 nm logic-die production. The imbalance is revealing: cutting-edge logic capacity mattered, but memory and packaging were already much closer to their limits.
The hardware has also become much more integrated. Nvidia's current Vera Rubin platform combines Rubin GPUs, Vera CPUs, NVLink switches, ConnectX networking, BlueField DPUs and other infrastructure into one rack-scale architecture. Nvidia said in its latest quarterly call that production shipments had already begun and that it had purchase orders from every major hyperscaler, AI cloud and system manufacturer it works with.
The slowdown now reaches far beyond the chip itself. The industry has become an exercise in making every piece of an enormous computer scale at roughly the same speed.
Are we still running out of AI compute?
Yes, usable AI compute is still tight, even though the shortage increasingly looks different from the old scramble for individual GPUs.
The useful unit today is a GPU that can actually be deployed. It needs HBM, advanced packaging, switches, network links, enough rack power, cooling equipment and somewhere in a data center to put it. A warehouse full of accelerators waiting for electrical capacity does not solve anyone's compute problem.
Demand also remains extraordinarily large. AWS recently said it plans to deploy another 2 million Nvidia Blackwell Ultra, Rubin and Rubin Ultra GPUs during 2027 and 2028, on top of the more than 1 million GPUs it had previously discussed adding. Nvidia's latest reported data-center quarter reached $62.3 billion of revenue, 75% above the same quarter a year earlier.
AMD is seeing the same appetite from a much smaller base. Anthropic has agreed to deploy up to 2 GW of AMD Instinct MI450 GPUs in Helios rack-scale systems, with the first gigawatt scheduled to begin deploying in the first half of 2027.
Those orders say more than a generic claim that "AI demand is strong." Three of the world's largest cloud and AI companies are planning capacity in units of millions of GPUs or gigawatts of accelerators. The difficult part is turning those commitments into running clusters quickly enough.
As this chart shows, and as featured in our AI chip market deck, search interest in AI chips has grown significantly
Has HBM become the biggest AI-chip bottleneck?
HBM is probably the clearest manufacturing bottleneck in AI chips right now.
The pressure has actually shifted toward memory. Epoch AI estimates that Nvidia, Google, AMD and Amazon went from consuming roughly two-thirds of global HBM supply in 2024 to about 90% in 2025. By the third quarter of 2025 the figure was around 92%, and by the fourth quarter it had reached roughly 97%.
Packaging followed the opposite trajectory. The same four companies consumed essentially all available CoWoS capacity around the turn of 2025, but TSMC's expansion brought their combined share down into the mid-80s later in the year. HBM kept getting tighter.
There is a technical reason. Every new accelerator generation is carrying more high-bandwidth memory because larger models, long contexts and inference workloads need enormous amounts of data kept close to the processor. Blackwell Ultra moved further in that direction, while Nvidia's current Rubin GPU uses HBM4.
SK hynix has now started mass shipments of HBM4 and says production will ramp further. That is encouraging, but it also shows how closely the AI-chip roadmap has become tied to the memory roadmap. Nvidia can finish designing a faster GPU and still be constrained by how many qualified HBM stacks suppliers can manufacture around it.
| HBM pressure | 2024 | 2025 |
|---|---|---|
| Share consumed by Nvidia, Google, AMD and Amazon | ~66% | ~90% |
| Share late in 2025 | — | ~97% in Q4 |
| Main direction | Tight | Much tighter |
If you want more recent data on this point, please see our latest AI chip market report.
Is advanced packaging still holding back AI chips?
Yes, advanced packaging is still a serious AI-chip constraint, although it is less brutally tight than it was at the start of the Blackwell ramp.
Modern accelerators are increasingly assemblies rather than one giant piece of silicon. Compute dies, HBM stacks and high-density interconnects have to be joined inside packages such as TSMC's CoWoS. That lets designers keep increasing the amount of compute and memory in one accelerator without making one impossible monolithic die.
The bottleneck became extreme around late 2024 and early 2025. Epoch AI estimates that the four largest US accelerator designers consumed 98% of CoWoS supply in one quarter and 99% in the next. TSMC then expanded estimated CoWoS capacity from roughly 39,000 wafers per month at the end of 2024 to around 66,000 by the end of 2025. Their combined consumption share subsequently fell to roughly 83–86%.
Today, that changes the ranking. Packaging has not suddenly become easy; TSMC is still having to support much larger and more complicated packages. But the evidence suggests HBM has overtaken generic CoWoS capacity as the sharper immediate supply problem.
Future packages will make the engineering harder again. More chiplets, more HBM and wider interconnects all increase package size and complexity. Packaging has become part of the performance roadmap itself, which means chip designers now depend on packaging advances almost as much as they depend on smaller transistors.
This chart, featured in our AI chip market deck, shows annual VC investment in AI chip startups
Can data centers actually power and cool the next generation of AI chips?
Power and cooling are becoming hard limits on how quickly the latest AI chips can be installed.
The scale is unusual even by data-center standards. Nvidia's recent rack-scale systems concentrate dozens of accelerators inside liquid-cooled architectures, and the company is redesigning electrical infrastructure around much higher power densities. What used to be a server-installation decision can now require new substations, busways, cooling loops and utility agreements.
The International Energy Agency expects electricity consumption from accelerated servers, mainly driven by AI, to grow around 30% a year through 2030 in its base case. Overall data-center electricity demand would reach roughly 945 TWh, about twice its 2024 level. Cooling and other infrastructure account for around one-fifth of the projected increase.
There is also a timing mismatch. The IEA notes that a data center can sometimes become operational within two or three years, while major energy infrastructure usually takes longer to plan and build. Semiconductor generations can move faster still.
That gap is becoming commercially important. A company can order thousands of excellent accelerators and then discover that the local grid cannot energize the campus on the desired schedule.
Cooling comes with the same problem. High-density racks increasingly rely on liquid cooling, forcing operators to install pumps, coolant distribution units, manifolds and heat-rejection infrastructure that many older facilities simply do not have.
For the newest AI systems, access to megawatts and cooling capacity can decide deployment speed just as much as access to GPUs. It sounds like infrastructure plumbing, but it can stop a cluster cold.
Is networking now limiting how fast AI chips can run?
Yes, networking has become one of the main reasons theoretical GPU performance fails to translate cleanly into real cluster performance.
A frontier training job can involve thousands of accelerators exchanging information constantly. If those accelerators spend too much time waiting for each other, buying faster GPUs produces disappointing returns.
Nvidia has built a large part of its advantage around solving that problem. Vera Rubin uses sixth-generation NVLink with 3.6 TB/s of scale-up bandwidth per GPU, alongside ConnectX-9 networking at 1.6 Tb/s per GPU and new Spectrum-X Ethernet systems. Nvidia's networking revenue also grew another 18% sequentially in its latest reported quarter, while Spectrum-X Ethernet revenue was 2.6 times higher than a year earlier.
Customers are increasingly buying the network as part of the AI computer rather than treating switches as generic infrastructure.
AMD is following the same route with Helios. Its strategy now combines Instinct GPUs, EPYC CPUs, scale-up links and scale-out networking in a rack-scale system. The up-to-2-GW Anthropic commitment is therefore also a test of whether AMD can make an entire non-Nvidia cluster work smoothly at hyperscale.
The competitive fight in AI chips is moving into the fabric connecting the accelerators. Peak GPU performance still matters, but idle GPUs waiting on communication are extremely expensive pieces of silicon.
This chart, featured in our AI chip market deck, shows how Nvidia is leading in AI chips
Can Moore's Law still keep AI chips getting faster?
Moore's Law still helps AI chips, but it can no longer produce the performance gains this industry wants on its own.
Leading-edge process nodes remain important. AMD's MI350 generation and newer Google TPUs have moved to 3 nm-class manufacturing, and future accelerators will keep using more advanced nodes where the economics make sense.
Designers are now pulling performance from several other places at once. Nvidia's Blackwell architecture joined two large compute dies inside one package. AMD has used chiplets extensively across CPUs and accelerators. HBM keeps moving more memory physically closer to the processor. AI arithmetic has also moved from FP32 toward BF16, FP8 and increasingly FP4 where model accuracy allows it.
Chiplets help because smaller dies can be easier to manufacture economically than one enormous monolithic die. They also let designers mix functions and process technologies. The price is harder packaging and harder communication between the pieces.
Each AI-chip generation increasingly looks like a systems-engineering project. More transistors remain useful, but packaging, memory, numerical precision, interconnects and software optimization now deliver a large part of the actual performance jump.
The industry can keep pushing beyond the slowdown in conventional transistor scaling. Doing it requires coordinating many more moving pieces than shrinking a die every couple of years.
If you want more recent data on this point, please see our latest AI chip market report.
Why can't AMD or another AI-chip company just break Nvidia's CUDA advantage?
Nvidia's CUDA advantage remains hard to break because a competitive GPU is much easier to build than a completely painless Nvidia replacement.
CUDA has nearly two decades of libraries, kernels, tools, documentation and developer habits behind it. Most AI developers never interact with all of that directly, but frameworks and production systems underneath them often do.
AMD has made real progress here. Its latest annual filing says ROCm supports more than 2 million models on Hugging Face and recorded a tenfold increase in downloads during 2025. AMD has also worked directly with PyTorch, Hugging Face, vLLM and SGLang to make popular workloads work out of the box.
The Anthropic agreement takes that further. Anthropic and AMD plan to work together on optimizing Claude for Instinct GPUs and improving ROCm. A customer willing to commit up to 2 GW of accelerators gives AMD a much stronger software-feedback loop than isolated benchmark wins ever could.
But the bar is higher than "Claude runs on AMD." Customers want kernels, libraries, monitoring tools, inference engines and debugging workflows to behave predictably without weeks of custom engineering.
Large hyperscalers can afford that work because saving a few percentage points on billions of dollars of infrastructure is valuable. Smaller AI companies have a different calculation. Paying more for Nvidia can still be cheaper than paying engineers to fight compatibility problems.
AMD is finally attacking that problem at a scale that matters. CUDA nevertheless remains one of Nvidia's strongest defenses today.
This chart, featured in our AI chip market deck, shows annual funding in AI chip startups
Will Google, Amazon and other custom AI chips eventually break Nvidia's dominance?
Custom AI chips will take a much larger share of hyperscaler workloads, but Nvidia can remain dominant even while that happens.
Google already provides the clearest proof. Epoch AI estimates Google controls roughly one-quarter of cumulative global AI compute, largely because of its own TPU fleet. Amazon has Trainium and Inferentia. Microsoft has Maia. Meta has MTIA. Broadcom has built a huge custom-accelerator business around hyperscaler demand.
At that scale, the economics make sense. A company spending tens of billions of dollars on computing can justify designing silicon for a workload it expects to run billions of times.
The catch is flexibility. AI workloads keep changing quickly. Attention implementations change, quantization improves, mixture-of-experts architectures evolve and inference increasingly includes long reasoning chains and agentic workloads. A programmable GPU gives customers more room to absorb those changes than a highly specialized accelerator built several years earlier.
Hyperscalers are already running both tracks at once. AWS is developing Trainium aggressively while simultaneously planning millions of additional Nvidia GPUs. Google keeps advancing TPUs while also offering Nvidia systems through Google Cloud.
We therefore expect custom silicon to eat into the workloads where hyperscalers know exactly what they need. Nvidia remains especially difficult to displace where customers need one platform that can run whatever important model architecture appears next.
| AI-chip approach | Where it is strongest | Main problem |
|---|---|---|
| Nvidia GPU | Broad, changing workloads | Cost and dependence on Nvidia |
| AMD GPU | Programmable alternative at large scale | Smaller software ecosystem |
| Google TPU | Google's internal stack and Cloud | Less universal |
| AWS Trainium | Large AWS-native AI workloads | Tied closely to AWS |
| Custom ASIC | Stable workloads at enormous scale | Less flexible when models change |
If you want more recent data on this point, please see our latest AI chip market report.
Is AI inference making the chip market more fragmented?
Yes, inference is making AI-chip design more fragmented because different AI workloads increasingly want different kinds of hardware.
Generating a short text answer, serving a million recommendation requests, producing video and running an agent through a long reasoning sequence put very different pressure on a processor. Some workloads are limited mainly by raw compute. Others depend more on memory capacity, bandwidth, latency or fast communication between chips.
Reasoning has made the distinction sharper. An AI system may generate a large amount of hidden computation before producing the answer a user sees, raising the amount of inference compute required per useful output.
Nvidia's current product design reflects that shift. Vera Rubin combines Rubin GPUs with separate infrastructure for CPUs, networking, storage and, following Nvidia's Groq deal, low-latency inference acceleration. Nvidia told investors that Vera Rubin could expand its revenue opportunity per gigawatt from roughly $25 billion with Blackwell to around $40 billion, precisely because more of the AI factory is being specialized.
Other companies can attack narrower pieces of the problem. Cerebras uses wafer-scale processors with unusually large on-chip memory. Groq built its original architecture around predictable, low-latency inference. Hyperscalers can tune internal chips around their own models and utilization patterns.
The idea of one universally "best AI chip" is getting less realistic. The interesting fight is over which architecture wins each large workload without becoming so specialized that the next model generation makes it obsolete.
This chart, featured in our AI chip market deck, compares the main business model options for AI accelerator chip companies
Are AI chips becoming too expensive to make economic sense?
AI chips are extremely expensive, but the real financial danger is paying for hardware that sits idle or becomes uneconomic faster than expected.
A high-end accelerator can cost tens of thousands of dollars, and complete rack-scale systems quickly reach millions. Yet a more expensive system can still be the cheaper choice if it serves substantially more useful tokens per hour.
Utilization is where the economics can fall apart. A theoretically powerful GPU running at 40% utilization can cost more per useful token than a slower device that stays busy. Memory capacity, networking, scheduling and software maturity all affect that utilization.
Hardware turnover adds another risk. Nvidia is now moving through Hopper, Blackwell, Blackwell Ultra and Rubin at an unusually fast cadence. Customers purchasing large clusters have to earn enough from them before newer systems change the cost curve again.
That helps explain why Nvidia increasingly sells efficiency in terms of tokens per megawatt and cost per token rather than only raw FLOPS. In its latest earnings call, the company claimed Vera Rubin delivers 30 times higher throughput per megawatt and 35 times lower token cost than Grace Blackwell Ultra on the workloads it highlighted. Those are Nvidia's own benchmark claims, so the exact multiples deserve caution, but the metric itself shows where the industry is heading.
The useful question for buyers today is fairly simple: how much reliable AI output will this system generate for every dollar spent on hardware, electricity and operation?
If you want more recent data on this point, please see our latest AI chip market report.
Is the AI-chip supply chain dangerously concentrated?
Yes, the AI-chip supply chain is still concentrated enough that problems at a handful of companies can affect the entire market.
Start with logic. TSMC manufactures the leading accelerators for Nvidia and AMD and also produces chips for several major custom-AI programs. Epoch AI estimates TSMC controls roughly 90% of global advanced-node fabrication.
Memory narrows the supplier list again. SK hynix, Samsung and Micron dominate HBM. At the frontier, customers cannot treat every HBM stack as interchangeable because each new generation has to meet very demanding bandwidth, thermal and packaging requirements.
Advanced packaging creates another dependency around TSMC and its CoWoS ecosystem. Even though CoWoS capacity has expanded significantly, the newest AI accelerators keep requiring larger and more complicated packages.
The concentration is layered. A company needs leading-edge logic, qualified HBM, advanced packaging and the substrates, equipment and materials feeding all three. Diversifying one layer does not make the whole chain resilient.
Geography makes this harder. Taiwan remains central to leading-edge logic and packaging, while South Korea plays an outsized role in advanced memory. Semiconductor companies are expanding capacity in the United States, Japan and elsewhere, but reproducing mature supplier networks and high manufacturing yields takes much longer than constructing an empty fab shell.
| AI-chip choke point | Main concentration | Why it is risky |
|---|---|---|
| Leading-edge logic | TSMC | One foundry is central to many frontier chips |
| HBM | SK hynix, Samsung, Micron | Only three major suppliers |
| Advanced packaging | TSMC/CoWoS ecosystem | Leading accelerators depend on it |
| Lithography and equipment | Small group of US, Dutch and Japanese suppliers | Difficult to substitute quickly |
This chart, featured in our AI chip market deck, shows how revenue is split across customer segments in the AI chip market
Are US-China restrictions creating two separate AI-chip industries?
US-China restrictions are pushing AI chips toward two increasingly separate ecosystems, but China still faces a much harder problem than simply designing its own GPU.
US controls now reach advanced accelerators, semiconductor-manufacturing equipment and HBM. The rules have changed several times as Washington has tried to close workarounds while still deciding which lower-performance products can legally reach Chinese customers.
That uncertainty directly affects product design. Nvidia previously created China-specific accelerators around US performance thresholds, only for the rules to change again. More recent US policy has moved some products, including Nvidia's H200 and AMD's MI325X, toward case-by-case licensing under specified conditions.
China has responded by pushing domestic alternatives much harder. Huawei's Ascend family is the most important example, and Chinese AI companies have become increasingly willing to optimize models around locally available hardware.
The manufacturing stack remains the harder obstacle. Building something that performs useful matrix multiplication is only one part of the job. China also needs competitive foundry processes, HBM, packaging, networking, development software and high manufacturing yields at large volumes.
Export controls have already affected global HBM flows. Epoch AI estimates Chinese buyers were still purchasing large amounts of HBM in 2024 before tighter restrictions sharply reduced that demand. US accelerator designers then absorbed nearly all of the industry's incremental supply as Blackwell and other memory-heavy chips ramped.
China can keep narrowing individual gaps, especially when enormous domestic demand justifies expensive engineering work. Rebuilding several tightly connected layers at the same time is what makes the catch-up difficult.
Why are AI-chip benchmarks getting harder to trust?
AI-chip benchmarks are becoming less useful on their own because a huge FLOPS number can tell us surprisingly little about how well a real AI service will run.
Precision is one obvious trap. FP4, FP8, BF16 and FP16 performance numbers cannot be compared casually. Running at lower precision can produce enormous throughput gains, but only when the model keeps acceptable quality.
Memory can overturn a headline comparison as well. A processor with lower peak compute but enough local memory to hold the workload may beat a faster chip that constantly moves data between accelerators.
Batch size changes the story again. Huge batches are excellent for maximizing aggregate throughput, while a chatbot user may care much more about the delay before the first token arrives. Long-context prefill, token-by-token decoding and model training each stress different parts of the system.
Large clusters add reliability to the equation. Once thousands of GPUs, switches, links, power supplies and cooling components are working together, hardware failures become routine events rather than freak accidents. Checkpointing, traffic rerouting and cluster scheduling can therefore change real performance dramatically.
We put more weight today on application-level throughput, latency, memory capacity, utilization, energy use and total cost together. A benchmark still tells us something useful about the chip; it tells us much less about the AI factory around it.
This chart, featured in our AI chip market deck, shows how AI accelerator chip technology has evolved over time
Can efficiency improvements eventually solve the AI-chip bottlenecks?
Efficiency will ease AI-chip bottlenecks, but current demand is growing fast enough to consume much of what those improvements free up.
The gains themselves are enormous. Lower precision lets accelerators perform more operations using less memory and power. Better kernels reduce wasted computation. Quantization shrinks models. Faster interconnects reduce waiting between GPUs. Hardware generations keep increasing performance per watt.
Yet the amount of AI we ask those systems to perform is rising at the same time. More people use AI products, context windows get longer, video models require heavy computation, agents make repeated model calls and reasoning systems can spend far more compute producing one answer.
The IEA's base case captures that effect well. Despite expected improvements in both hardware and software efficiency, electricity consumption from accelerated servers is still projected to rise roughly 30% a year through 2030.
We can see the same appetite in actual purchasing plans. As pointed out above, AWS is simultaneously improving its own Trainium chips and planning millions more Nvidia GPUs, while Anthropic has committed to a potential gigawatt-scale AMD deployment. Better chips are encouraging companies to deploy more AI rather than declare that they finally have enough compute.
Efficiency is essential for keeping AI economics from becoming much worse. For now, it does not look capable of making compute abundant.
So what are the biggest challenges facing AI chips now?
The biggest AI-chip challenges now are HBM, power, networking, advanced packaging, software and supply-chain concentration, with raw processor design increasingly sitting inside that larger systems problem.
HBM deserves the first spot today because the latest evidence shows demand tightening even after packaging capacity started catching up. The four largest US accelerator designers were consuming roughly 97% of global HBM supply by late 2025, and newer generations such as Rubin are already moving to HBM4.
Power and cooling come next because semiconductor companies can scale performance much faster than utilities can build infrastructure. The IEA still expects accelerated-server electricity use to grow around 30% annually, while the latest AI systems push far more compute into each rack.
Networking has become another core constraint. Nvidia's latest quarter showed Spectrum-X Ethernet revenue growing 2.6 times year over year, which fits what the architectures themselves are telling us: large AI systems increasingly win or lose on how efficiently thousands of processors communicate.
Advanced packaging remains difficult, but we would rank it slightly below HBM today because TSMC's capacity expansion has already created more headroom than existed during the worst CoWoS squeeze.
Then comes software. AMD can build competitive accelerators and custom chips can beat GPUs on specific workloads, yet Nvidia still benefits from the combination of CUDA, networking and a mature rack-scale platform. The challenge for competitors is making an alternative just as easy to operate.
Supply-chain concentration sits over all of this. TSMC remains central to leading-edge logic and packaging, three companies dominate HBM, and export controls are making that concentrated chain more politically complicated.
AI-chip progress itself is still moving extremely fast: Vera Rubin has already entered production, HBM4 is shipping and hyperscalers are placing huge next-generation orders. The harder problem is keeping memory, networks, factories, grids, cooling systems and software moving fast enough to make all that new silicon useful.
That is where the AI-chip race is being decided now.
If you want more recent data on this point, please see our latest AI chip market report.
In our AI chip market deck, we identify pain points entrepreneurs should prioritize
OUR METHODOLOGY
The question behind this analysis — what are the biggest challenges facing AI chips now? — does not have a clean answer from any single metric. We broke it into the main dimensions that can constrain AI compute in practice: semiconductor manufacturing, memory and packaging, data-center power and cooling, networking, software, economics, supply-chain concentration, and the rise of alternative chip architectures.
For each dimension, we looked for the freshest evidence showing what is happening in the market rather than what is merely expected to happen. We gave particular weight to production and shipment data, capacity changes, large deployment commitments, company financials, infrastructure requirements and observed technology transitions. Forecasts were used where they were the clearest evidence, especially for future electricity demand.
We separated different kinds of constraint instead of treating every AI-chip problem as equivalent. Some factors limit how many accelerators can be manufactured; others determine how quickly those accelerators can be installed, how efficiently they work together once deployed, or how easily customers can switch between competing platforms.
Where companies do not publish enough information to measure a market directly, we used transparent reconstruction work based on disclosed chip volumes, component requirements, manufacturing capacity and supply-chain data. We prioritized estimates where the underlying methodology and assumptions could be inspected, then checked whether the direction of those estimates was consistent with disclosures from manufacturers and suppliers.
We treated company performance claims differently from operating evidence. Vendor benchmarks help show which technical and economic metrics the industry is optimizing around, but headline performance multiples alone were not used to decide which architecture or system is stronger. We looked more broadly at memory, networking, utilization, power, software maturity and workload-level economics.
Finally, we formed the overall judgment by aggregating the evidence across these dimensions. Our ranking gives more weight to constraints that are currently binding across large parts of the industry, directly affect deployable or useful AI compute, and continue to tighten faster than capacity is expanding.
Key sources used for this analysis include Epoch AI's AI-chip supply-chain constraints analysis, Epoch AI's AI Chip Components methodology, the underlying AI Chip Components dataset, Epoch AI's work on Google's TPU compute base, Nvidia's latest quarterly results, Nvidia's latest earnings-call transcript, Nvidia's Vera Rubin NVL72 specifications, AWS on its additional Nvidia GPU deployment plans, AWS on Trainium3, AMD and Anthropic on the planned 2 GW Instinct deployment, AMD's 2025 Form 10-K, SK hynix on HBM4 shipments, Micron on HBM4 high-volume shipments, TSMC on CoWoS capacity expansion, the IEA's Energy and AI analysis, Google on its eighth-generation TPUs, the U.S. Bureau of Industry and Security on China licensing policy, and ASML's 2025 Annual Report.
This chart, featured in our AI chip market deck, shows how revenue is split by region across Europe, Asia, North America, Africa, and South America in the AI chip market
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