Semiconductors: what are the biggest unsolved problems?
Whether you're building or investing in the semiconductor market, our report covers everything you need to know: the players, the money, and what's coming next.
Summary
Semiconductors: what are the biggest unsolved problems? The most serious are energy-efficient data movement, memory bandwidth, advanced manufacturing costs, chip packaging, and the concentration of critical supply chains. These constraints increasingly determine how fast computing can improve and how expensive that progress becomes.
The industry is growing faster than many of its underlying technologies can comfortably support. Global semiconductor sales reached $791.7 billion in 2025, up 25.6%, but higher spending doesn't automatically translate into cheaper computing or more available chips.
Moore's Law is becoming an economic problem as much as a physical one. TSMC's 2-nanometer process is scaling commercially, yet every new manufacturing generation requires more expensive equipment, engineering, and defect control. Smaller transistors no longer guarantee proportionally cheaper performance.
The most fundamental technical bottleneck may be moving information rather than calculating with it. AI processors can perform enormous numbers of operations, but transferring data between computing units, memory, and separate chips consumes energy and creates delays that raw processing power cannot eliminate.
High-bandwidth memory is where that problem becomes commercially visible. TrendForce expects HBM supply constraints through 2027, with a projected 121% increase in blended selling prices. Some accelerator designers may even accept more expensive memory configurations per gigabit to manufacture more complete processors.
Chiplets solve part of the manufacturing problem while creating another. Dividing large processors into smaller dies can improve yields and allow different manufacturing technologies to work together, but packaging, testing, communication, and cooling become more complicated. The industry is moving some of its hardest problems from the silicon die into the package.
Electricity is emerging as a limit that semiconductor companies cannot solve alone. The IEA projects global data center consumption rising from approximately 485 TWh in 2025 to 950 TWh by 2030. Better processors help, but grid connections, power infrastructure, and cooling capacity increasingly determine where AI computing can actually be deployed.
Manufacturing efficiency and environmental sustainability are moving in different directions. TSMC reduced water consumption per unit of manufacturing activity in 2025, yet its total water usage increased 17.1%. The industry can become more efficient per chip while consuming more resources overall.
The supply chain remains dangerously concentrated. Taiwan dominates leading-edge foundry manufacturing, ASML is the sole commercial EUV lithography supplier, and advanced memory production depends on a small group of manufacturers. Building factories in more countries improves resilience, but replicating an entire semiconductor ecosystem is much harder than constructing a fab.
Older technologies are another overlooked vulnerability. Automotive, industrial, medical, and power-management chips often depend on mature processes that are economical and reliable precisely because they haven't moved to the latest nodes. Investment in advanced AI processors won't automatically protect these supply chains.
Our conclusion is that the next major improvement in computing economics will come from solving several connected bottlenecks, not simply shrinking transistors. In the near term, HBM and advanced packaging deserve the most commercial attention. Over the longer term, the winners will be those delivering the most useful computing performance per dollar and per watt, reliably and at scale.
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A good product starts with a real problem. In our report covering the semiconductor market, we show you the ones customers still live with.
Why are semiconductor problems getting worse when the industry is growing so fast?
The semiconductor industry is growing at record speed, but building faster, cheaper, and more efficient chips is becoming harder with every new generation.
According to the Semiconductor Industry Association, worldwide chip sales reached $791.7 billion in 2025, up 25.6% from $630.5 billion in 2024. Logic semiconductors generated $301.9 billion, while memory contributed $223.1 billion. Together, these two categories accounted for roughly two-thirds of global semiconductor sales.
The growth has pushed manufacturers into an extraordinary investment cycle. In its latest industry outlook, SEMI projected that spending on equipment for 300-millimeter semiconductor fabs would reach $149 billion in 2026 and $227 billion by 2029. That's an increase of 52% in three years. The organization also expects construction to begin on 38 new 300-millimeter fabs or production lines across 2026 and 2027.
Yet more investment doesn't guarantee cheaper computing. TSMC is manufacturing 2-nanometer chips, ASML is developing increasingly sophisticated lithography systems, and Nvidia and AMD are integrating more processing power and memory into their accelerators. Each improvement creates new problems involving heat, electricity, manufacturing yield, or the speed at which information moves between components.
A faster processor may need more memory bandwidth. More memory requires expensive packaging. Larger packages create cooling difficulties. Solving those difficulties raises the cost of the finished product.
Is Moore's Law finally reaching its physical limits?
Moore's Law is still alive, but shrinking semiconductor transistors no longer guarantees the cheap, predictable performance improvements that made modern computing possible.
For decades, manufacturers improved processors by placing more transistors on a chip while reducing the cost of individual transistors. That approach became increasingly difficult as electrical leakage, resistance, quantum effects, and heat started limiting the benefits of smaller components.
TSMC's transition to 2-nanometer manufacturing shows how much the technology has changed. The company now uses gate-all-around nanosheet transistors, replacing the FinFET structures used in earlier generations. Samsung introduced gate-all-around technology with its initial 3-nanometer process, while Intel developed its own RibbonFET architecture for Intel 18A.
These companies are pursuing similar architectural changes because conventional transistor structures have become increasingly difficult to improve.
And the demand is real. TSMC's third-quarter 2026 results showed that 2-nanometer technology had reached 8% of wafer revenue, up from 3% in the previous quarter. Meanwhile, 3-nanometer and 5-nanometer technologies represented another 33% and 28%, respectively. Advanced nodes of 7 nanometers and below accounted for 79% of total wafer revenue.
The problem is that transistor density and economic efficiency are no longer improving at the same pace. More transistors can fit into a given area, but the equipment, materials, engineering work, and manufacturing steps needed to produce them have become substantially more complicated.
There's also a distinction between the names of manufacturing nodes and their actual physical dimensions. A commercial 2-nanometer process doesn't mean that every transistor feature measures exactly two nanometers. Node names have become labels for successive manufacturing generations.
The era of easy scaling is over. Moore's Law may continue in terms of transistor density, but the economics that made it so powerful are much harder to sustain.
If you want more recent data on this point, please see our latest semiconductor industry report.
If you build or invest in the semiconductor market, you need to know which business models pay off now and which ones are fading. That's why our report covering it has a whole section on it.
Why are smaller semiconductor chips so expensive and difficult to manufacture?
Advanced semiconductor manufacturing is becoming dramatically more expensive because each new generation needs increasingly complicated equipment, additional processing steps, and tighter control over defects.
ASML offers one of the clearest examples. The Dutch company generated €32.7 billion in revenue in 2025 and spent approximately €4.7 billion on research and development. It remains the only commercial supplier of extreme ultraviolet lithography systems used for manufacturing the most advanced logic chips.
Its newer High-NA EUV systems are designed to print smaller semiconductor features with fewer repeated patterning steps. ASML's EXE:5200B targets throughput of 175 wafers per hour, approximately 60% higher than the earlier EXE:5000 generation.
That productivity improvement is essential. A machine that produces finer patterns but processes too few wafers can make the resulting chips prohibitively expensive.
The costs extend well beyond lithography. Manufacturers must invest in advanced deposition equipment, etching systems, inspection tools, materials, and process development. Each additional manufacturing step creates another opportunity for defects.
Manufacturing yield is particularly important. Yield measures how many manufactured chips meet the required specifications. A silicon wafer can contain hundreds or thousands of individual chips, depending on their size. Some will fail testing because of defects or variations introduced during manufacturing.
Under a simplified random-defect model, the probability of producing a defect-free chip decreases exponentially as its area increases. A large AI accelerator is therefore more exposed to manufacturing defects than a much smaller processor produced using the same technology.
This helps explain the appeal of chiplets. AMD has used separate dies across multiple Ryzen and EPYC processor generations, allowing manufacturers to build large processors from smaller components rather than relying entirely on one enormous piece of silicon.
TSMC's recent results show that advanced manufacturing is commercially viable. Its 2-nanometer share of wafer revenue increased from 3% to 8% between the second and third quarters of 2026. Over the same period, quarterly revenue rose from $40.2 billion to $46.72 billion.
However, TSMC doesn't publicly disclose a complete set of comparable defect-yield figures for every process and customer product. We therefore know that 2-nanometer manufacturing is scaling rapidly, but we cannot reliably calculate the proportion of large advanced chips that pass testing from the company's financial results alone.
SEMI's latest forecast makes the scale of investment clearer. Worldwide spending on 300-millimeter fab equipment is expected to increase 31% in 2026, reaching $149 billion, before climbing to $227 billion in 2029.
An AI processor selling for thousands of dollars can justify a manufacturing technology that would make little sense for a $2 automotive controller. That's why chipmakers increasingly combine advanced logic with components manufactured on older, less expensive processes.
Are the wires inside semiconductors becoming a bigger problem than the transistors?
The microscopic wires connecting semiconductor transistors are becoming a major performance bottleneck, especially as processors pack more components into smaller spaces.
A processor containing billions of transistors needs an enormous network of connections to distribute electrical power and move information. As those connections become narrower, electrical resistance generally increases. Closely spaced wires also create unwanted electrical interactions and delays.
Intel's PowerVia technology addresses part of the problem by moving power distribution to the backside of the silicon wafer. This separates power delivery from some of the signal-routing structures. TSMC is developing a related approach for its A16 manufacturing generation.
Research organization imec is investigating alternative materials, new interconnect structures, and vertically stacked transistor architectures.
In research published during 2026, imec reported that improvements in backside contacts reduced access resistance from 1,753 to 378 ohm-micrometers in one experimental structure. The proportion of bottom transistors surviving the relevant processing steps increased from 45% to 85%.
Those numbers come from a specific research experiment rather than commercial production. Still, it's a big improvement, and it shows how much progress can come from redesigning electrical connections.
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Why does moving data consume so much energy in AI chips?
Moving data is now one of the biggest efficiency problems in AI semiconductors because processors can perform calculations much faster than information can always be delivered to them.
Modern AI accelerators are designed to perform enormous numbers of mathematical operations. But those calculations require a constant supply of model parameters, intermediate results, and other data stored in different types of memory.
When information arrives too slowly, computing units sit idle even though the processor is technically capable of performing more operations.
Moving information also consumes energy, and the cost depends heavily on where the information is stored. Accessing a nearby register is much cheaper than repeatedly transferring data from external memory. Communication between separate processors can be more expensive still.
Nvidia's high-performance accelerators use HBM positioned close to the processor. AMD combines advanced packaging with stacked memory in its Instinct products. Google's tensor processing units similarly rely on tightly designed memory systems and interconnects.
The same problem appears inside individual chips. Larger caches can reduce expensive memory accesses, but they consume valuable silicon area. More memory bandwidth can improve utilization, but it raises packaging complexity and power requirements.
Different workloads also move data differently. Training a large AI model, running inference, processing graphics, and performing scientific simulations all place different demands on memory.
We consider energy-efficient data movement the most fundamental technical problem in modern high-performance semiconductors. Building more powerful computing units achieves little if keeping them supplied with information becomes disproportionately expensive.
If you want more recent data on this point, please see our latest semiconductor industry report.
Is high-bandwidth memory the biggest bottleneck for AI chips right now?
High-bandwidth memory is currently one of the most serious bottlenecks in AI chip production, and the shortage is already influencing how manufacturers design future accelerators.
HBM stacks multiple DRAM dies vertically and connects them through extremely dense interfaces. It provides much higher bandwidth than conventional memory modules while sitting close to the processor.
That makes it essential for products such as Nvidia's Blackwell accelerators and AMD's Instinct processors.
The difficulty comes from manufacturing and integration. HBM requires advanced DRAM production, stacking, specialized packaging, and additional testing. Increasing memory production doesn't immediately solve the problem because conventional DRAM and HBM compete for some of the same manufacturing capacity.
TrendForce reported in September 2026 that HBM supply was likely to remain constrained through 2027. Its forecast projected a 121% year-over-year increase in the blended average selling price of HBM in 2027, reflecting tight supply and a shift toward more expensive HBM4 products.
One particularly interesting finding was that some GPU and AI accelerator developers were considering reducing the number of memory layers per stack.
Using eight-layer stacks instead of twelve-layer configurations can make a limited supply of memory dies available to more processors. However, TrendForce estimated that eight-layer products could cost approximately 10-20% more per gigabit because fixed components are spread across less memory capacity.
Manufacturers may therefore accept a higher cost per gigabit to produce more complete AI accelerators.
Meanwhile, SEMI projected that equipment investment in 300-millimeter memory fabs would reach $52 billion in 2026, up 29%.
New equipment still needs to be installed, qualified, and brought to acceptable yields before that investment translates into additional memory supply.
| Memory technology | Main advantage | Biggest limitation |
|---|---|---|
| SRAM | Extremely fast access | Expensive and uses substantial chip area |
| DDR5 | Relatively affordable system memory | Lower bandwidth than HBM |
| LPDDR5X | Efficient power consumption | Bandwidth and capacity trade-offs |
| HBM3 | High bandwidth close to processors | Expensive packaging and stacking |
| HBM3E | Higher bandwidth and capacity | Thermal and manufacturing complexity |
| HBM4 | Wider interfaces and more bandwidth | Production yields, cost, and supply |
| GDDR7 | High bandwidth for graphics and accelerators | Power consumption and signal integrity |
| NAND flash | Dense, low-cost data storage | Much slower than working memory |
When you build or invest in the semiconductor market, you need clarity, not confusion. In our document detailing everything you need to know about semiconductor, we always try to put numbers on and quantify whatever is usually vague and confusing.
Can chiplets and advanced packaging solve the problem of making larger and faster processors?
Chiplets and advanced packaging are already helping manufacturers build processors that would be difficult or expensive to produce as single silicon dies, but connecting and testing all those components remains a major challenge.
Instead of manufacturing every function on one large chip, companies can combine several smaller dies inside a package.
AMD showed the commercial value of this approach through its Ryzen and EPYC processor families. Intel has developed technologies such as EMIB and Foveros, while TSMC offers advanced packaging platforms including CoWoS, which is widely used to connect powerful AI processors with high-bandwidth memory.
Smaller dies can improve manufacturing yields because they are less exposed to random defects. They also allow engineers to combine components produced using different manufacturing processes.
A company might manufacture its computing cores on an advanced node while using an older, cheaper process for input/output functions.
But splitting a processor creates new problems. Information must travel between chiplets, requiring fast connections that consume electricity, introduce latency, and occupy space.
Manufacturing and testing are becoming increasingly demanding as well. An advanced package can contain multiple logic dies, memory stacks, interposers, substrates, and thousands of electrical connections. A defective connection can compromise an assembly containing several otherwise functional and expensive components.
SEMI's July 2026 forecast gives us an indication of how quickly testing requirements are growing. Global semiconductor test equipment sales are expected to increase 31% to $15.3 billion in 2026, following 55.3% growth in 2025.
That represents approximately 104% cumulative growth over two years, assuming the forecast is realized.
Industry standards such as Universal Chiplet Interconnect Express, or UCIe, are trying to make it easier to combine components from different suppliers. However, electrical compatibility doesn't guarantee that independently developed chiplets will work together reliably. Packaging dimensions, thermal limits, power delivery, and software support must also align.
Could cooling and electricity shortages slow down the growth of AI chips?
Cooling and electricity availability are becoming serious limits on AI semiconductor deployment because newer processors concentrate more heat into smaller spaces while data centers require increasingly large power supplies.
The semiconductor industry has faced thermal problems before.
During the 2000s, processor clock speeds stopped increasing as quickly because higher frequencies and power consumption generated too much heat. Manufacturers responded by developing multicore processors and improving energy efficiency.
AI infrastructure is bringing the problem back on a much larger scale.
According to the International Energy Agency, the power density of AI servers increased elevenfold between 2020 and 2025. The organization expects another fourfold increase by 2027.
Traditional air cooling is becoming impractical for some high-density configurations. Direct liquid cooling is increasingly used because liquids can transfer heat more effectively than air.
However, cooling the rack is only part of the challenge.
Heat must travel from the transistors through silicon, packaging materials, thermal interfaces, and cooling structures. When several chips are stacked vertically, internal components may have limited access to cooling surfaces.
Researchers are studying microfluidic channels, improved thermal interface materials, and alternative packaging structures that bring cooling closer to heat-generating components.
Beyond cooling, electricity supply is becoming a serious obstacle.
The International Energy Agency estimates that data centers consumed approximately 485 terawatt-hours of electricity worldwide in 2025.
Its latest outlook projects consumption of around 950 terawatt-hours by 2030, an increase of roughly 96%. Electricity consumption by AI-focused data centers is expected to triple over the same period.
To put the increase in perspective, an additional 465 terawatt-hours per year is equivalent to an average continuous electrical load of approximately 53 gigawatts.
Data centers need transmission lines, substations, transformers, local grid connections, and reliable power supplies. Some facilities may face years of delays even when the required servers and processors are available.
The constraint is particularly important because computing infrastructure is concentrated in specific regions. A country can have sufficient total electricity generation while individual locations struggle to connect new facilities to the grid.
Microsoft, Amazon, Google, and Meta are responding by investing in power infrastructure and entering long-term electricity supply arrangements.
The semiconductor industry can help by reducing the amount of energy required for each computation. But more efficient chips may also encourage companies to run more workloads, increasing total consumption.
We expect access to electricity to become a bigger factor in determining where advanced AI computing is built. A processor can be technically excellent and commercially available, yet still be difficult to deploy if the necessary power infrastructure isn't there.
If you want more recent data on this point, please see our latest semiconductor industry report.
In our report covering the semiconductor market, we look at what the winners do differently, so you can learn from the best instead of guessing.
Can semiconductor manufacturers reduce pollution while making more chips?
Semiconductor manufacturers are improving resource efficiency, but production growth is making it difficult to reduce their total environmental footprint.
Modern chipmaking requires substantial electricity, ultrapure water, process gases, chemicals, and manufacturing equipment. Advanced processes can add steps or increase resource requirements even when individual transistors become more efficient.
TSMC's environmental disclosures provide a concrete example.
According to its 2025 annual report, total water usage increased from 129 million cubic meters in 2024 to 151 million cubic meters in 2025.
That's a 17.1% increase in one year.
At the same time, water usage per 12-inch wafer-equivalent mask layer fell from 161.0 to 153.3 liters, an improvement of approximately 4.8%.
There is an additional complication. TSMC reported that its 2025 unit water consumption remained 8.8% above its 2010 baseline, meaning the company had not achieved its corresponding annual reduction target.
Water is particularly important because semiconductor fabs require extremely clean processing conditions. Many manufacturing steps involve washing or treating wafers, often with ultrapure water.
Electricity and process gases create separate environmental challenges. Certain fluorinated gases used in semiconductor manufacturing have very high global warming potential, making effective capture and treatment important.
Companies are investing in water recycling, gas abatement, renewable electricity, and more efficient equipment.
| Environmental indicator | Evidence | Remaining problem |
|---|---|---|
| Total water usage | TSMC used 129M m³ in 2024 | Increased to 151M m³ in 2025 |
| Water efficiency | TSMC used 161.0 L per wafer-equivalent mask layer in 2024 | Improved to 153.3 L in 2025, but missed its reduction target |
| Water recycling | TSMC reported extensive water recycling across its fabs | Scaling reuse as new facilities open |
| Manufacturing electricity | Advanced fabs need reliable electricity around the clock | Securing enough low-carbon power |
| Fluorinated process gases | Some have extremely high warming potential | Improving capture and replacement |
| Chemical waste | Manufacturing requires numerous chemicals | Recovering and treating waste safely |
| Advanced lithography | Some technologies reduce repeated patterning steps | Controlling total process energy consumption |
| New factories | Global fab construction is increasing | Managing construction and startup resource demand |
Is the semiconductor industry too dependent on Taiwan?
The semiconductor industry remains heavily dependent on Taiwan for advanced chip manufacturing, and the current wave of new factories abroad hasn't eliminated that risk.
TSMC manufactures leading-edge processors for companies including Nvidia, AMD, and Apple. Its combination of technical expertise, manufacturing capacity, and customer relationships is extremely difficult to reproduce.
The company's third-quarter 2026 financial results show just how strong that position remains.
TSMC generated $46.72 billion in revenue, up 41.2% year over year in US dollars, with a gross margin of 66.4%. Advanced technologies of 7 nanometers and below accounted for 79% of wafer revenue.
The company also demonstrated how quickly new manufacturing generations can scale, with its 2-nanometer revenue share increasing from 3% to 8% in a single quarter.
That concentration creates a strategic vulnerability. A serious disruption affecting Taiwanese semiconductor manufacturing could interrupt production for companies across cloud computing, consumer electronics, telecommunications, and industrial technology.
TSMC is expanding internationally, including manufacturing operations in Arizona and Japan. Samsung operates important manufacturing facilities in South Korea and the United States, while Intel is developing its foundry business.
Advanced manufacturing requires specialized equipment suppliers, engineering teams, materials, packaging facilities, and production experience. Moving some wafer production overseas doesn't automatically reproduce the wider ecosystem.
Other bottlenecks are concentrated in different countries. ASML is the sole commercial EUV lithography supplier, while advanced DRAM and HBM production is dominated by a small group of companies, including SK hynix, Samsung, and Micron.
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Why can't the United States and Europe just manufacture all their own chips?
The United States and Europe can manufacture more semiconductors domestically, but becoming fully self-sufficient would be extremely expensive and would still leave major technical dependencies.
A competitive manufacturing operation needs equipment, materials, engineering expertise, specialized suppliers, customer relationships, and years of experience improving yields.
The United States is investing heavily through the CHIPS and Science Act. TSMC, Intel, Samsung, and Micron have announced major American manufacturing projects.
However, building schedules have been adjusted across several projects. A 2026 Congressional Research Service report identified issues including workforce availability, demand conditions, funding uncertainty, and environmental reviews.
The workforce challenge is especially important.
A study published by the Semiconductor Industry Association and Oxford Economics in 2023 projected that approximately 67,000 semiconductor-related technical positions in the United States could remain unfilled by 2030 if education and training trends continued unchanged.
That represented approximately 58% of the projected new semiconductor jobs.
The forecast is several years old and should not be treated as a measured current shortage. Nevertheless, it illustrates the scale of the talent pipeline needed to support factory expansion.
Europe has different strengths. ASML leads in advanced lithography equipment, while companies such as Infineon, STMicroelectronics, and NXP have strong positions in automotive, industrial, and specialized semiconductors.
These capabilities give Europe considerable importance in the global supply chain, even without leading the most advanced contract manufacturing market.
Trying to manufacture every semiconductor category domestically would require duplicating enormous amounts of infrastructure, often without enough local demand to operate it efficiently.
We think regional specialization combined with diversified manufacturing is a more realistic goal than complete semiconductor independence. The real challenge is reducing dangerous single points of failure without making the entire industry dramatically more expensive.
If you want more recent data on this point, please see our latest semiconductor industry report.
Why is designing a new semiconductor chip so expensive?
Designing advanced chips is becoming increasingly expensive because engineers must verify billions of components and their interactions before committing to a manufacturing process that leaves little room for mistakes.
Modern semiconductor design requires architecture development, circuit simulation, timing analysis, power optimization, verification, physical layout, and manufacturing preparation.
A defect discovered after fabrication can require an expensive redesign and another manufacturing cycle.
The challenge becomes much harder at advanced nodes because electrical resistance, heat, manufacturing variability, and physical layout constraints interact in increasingly complicated ways.
Companies such as Synopsys, Cadence, and Siemens EDA provide software that helps designers manage these challenges. Their tools automate parts of the process, but chip development still requires substantial engineering expertise and computing resources.
A relatively simple analog component manufactured using a mature process can be developed with far fewer resources than a leading-edge AI accelerator containing billions of transistors and multiple memory interfaces.
Chiplets can reduce some manufacturing risks by allowing companies to reuse existing components. RISC-V can lower dependence on proprietary instruction-set licenses. AI-assisted design tools may help engineers explore circuit layouts and identify errors more efficiently.
However, none of those approaches eliminates the need for extensive validation.
Security makes verification even more demanding.
Hardware vulnerabilities such as Spectre and Meltdown, publicly disclosed in 2018, demonstrated how processor optimizations could create unexpected security weaknesses. Some mitigations required software or firmware changes that could affect performance.
The growth of chiplets and heterogeneous processors introduces more interfaces that designers must verify.
Smaller semiconductor companies therefore face a difficult choice: spend heavily on custom development to differentiate their products or rely on existing architectures and reusable components that competitors can also access.
In our market report about semiconductors, we always try to gather several sources and make estimates that make sense, so you can work with solid numbers.
Why are older semiconductor chips still so difficult to replace?
Older semiconductor technologies remain essential because many products need reliable, inexpensive chips that can operate for years, rather than the smallest and fastest transistors available.
Automotive controllers, industrial sensors, power-management circuits, medical equipment, and numerous embedded systems often rely on mature manufacturing processes.
Some of these chips need to handle higher voltages, tolerate extreme temperatures, or remain available for more than a decade.
Moving them to a newer manufacturing process may provide little benefit while introducing considerable redesign and qualification costs.
The automotive chip shortages of 2020-2022 showed how serious this dependence can become. Shortages of relatively inexpensive controllers and other components interrupted the production of vehicles worth tens of thousands of dollars.
The economics are awkward for manufacturers.
Demand for mature-node chips is often less exciting than demand for AI processors. Yet adding production capacity requires expensive equipment and long construction schedules. Manufacturers must consider the risk that a shortage today could turn into excess capacity several years later.
SEMI's 2026 outlook for 200-millimeter semiconductor fabs projected installed capacity of approximately 7.7 million wafers per month, demonstrating the continued scale of these manufacturing technologies.
Mature-node chips also include highly specialized products where semiconductor properties matter more than transistor density.
Silicon carbide devices, for example, can offer advantages in high-voltage power conversion, while gallium nitride can perform well in compact power electronics and high-frequency applications.
Both technologies face manufacturing cost, reliability, and qualification challenges. Their growth is more likely to expand the semiconductor industry's range of materials than replace conventional silicon across every application.
Can quantum computing and optical chips eventually replace silicon?
Quantum computing and optical chips could solve specific problems that conventional semiconductors handle poorly, but neither technology is close to replacing silicon across everyday computing.
Quantum computers use quantum states to perform certain kinds of calculations differently from classical processors.
The potential advantages are substantial for selected problems, including quantum simulation and particular mathematical algorithms. However, building reliable systems remains extremely difficult.
Qubits are sensitive to noise, and errors accumulate during calculations. Quantum error correction can address some of these issues, but it generally requires many physical qubits to create reliable logical qubits.
Increasing the number of qubits in a machine therefore doesn't automatically translate into a comparable increase in useful computing capability.
Optical computing faces a different set of challenges.
Light can carry information at high bandwidth, making photonics attractive for communication between processors, memory systems, and data centers.
Silicon photonics is already commercially relevant in optical communication. However, replacing conventional electronic calculations with optical operations is more difficult because computers also need memory, programmability, nonlinear operations, and reliable conversion between different signal formats.
Optical interconnects could reduce communication bottlenecks in advanced computing systems. Quantum processors may eventually outperform classical machines on selected problems.
For now, both technologies look more likely to complement conventional chips than replace them. Silicon still has an enormous advantage in manufacturing scale, cost, and reliability.
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What are the biggest unsolved semiconductor problems today?
The biggest unsolved semiconductor problems today are energy efficiency, memory bandwidth, manufacturing cost, advanced packaging, and supply-chain concentration. Together, they threaten to make computing more expensive and harder to scale even while transistor technology continues improving.
For decades, making smaller transistors was the most important source of progress. Today, the performance of a computing system increasingly depends on how efficiently its processors communicate with memory, how much electricity they consume, and whether manufacturers can build and connect those components at acceptable costs.
The evidence also shows that these problems are developing at different speeds.
TSMC's third-quarter 2026 results demonstrated rapid adoption of 2-nanometer manufacturing. Yet TrendForce's latest forecast suggests high-bandwidth memory will remain constrained through 2027, with substantially higher prices.
Meanwhile, SEMI expects extraordinary growth in manufacturing equipment spending, and the International Energy Agency projects that data center electricity consumption will nearly double between 2025 and 2030.
Semiconductor processing capability is advancing quickly, while memory supply, electricity infrastructure, and manufacturing integration are struggling to keep pace.
The ranking below reflects our assessment of current technical severity, commercial impact, and the availability of practical solutions. It isn't a ranking of scientific difficulty alone.
| Unsolved problem | Why it's difficult | Current evidence | Our assessment |
|---|---|---|---|
| Energy efficiency | More computing generates additional heat and electricity demand | IEA projects data center consumption near 950 TWh by 2030 | Critical |
| Memory bandwidth and capacity | AI processors need faster access to enormous amounts of data | TrendForce expects HBM constraints through 2027 | Critical |
| Data movement | Communication consumes energy and creates delays | Backside power delivery and interconnect redesign remain active research areas | Critical |
| Advanced manufacturing cost | Each new node requires increasingly expensive equipment and processes | SEMI projects $227B in annual 300mm fab equipment spending by 2029 | Critical |
| Advanced packaging | Combining processors and memory creates new manufacturing risks | Semiconductor test equipment sales projected to rise 31% in 2026 | Critical |
| Supply-chain concentration | Critical technologies depend on a limited number of suppliers | Advanced foundry, EUV lithography, and HBM production remain concentrated | Critical |
| Manufacturing yield | Defects can make large processors uneconomical | Advanced-node production is scaling, but product-level yields remain largely private | High |
| Cooling | Chip and rack power density is increasing rapidly | IEA reports elevenfold growth in AI server power density from 2020 to 2025 | High |
| Semiconductor workforce | Complex factories need highly specialized engineers and technicians | US industry study projected 67,000 potentially unfilled technical positions by 2030 | High |
| Design complexity and security | Larger architectures require extensive verification | Hardware vulnerabilities and integration complexity remain major challenges | High |
| Environmental sustainability | Manufacturing growth can outweigh efficiency improvements | TSMC's total water usage increased 17.1% in 2025 | High |
| Mature-node resilience | Essential industries depend on older production technologies | Large 200mm manufacturing base remains economically important | High |
| Alternative materials | New materials have manufacturing and reliability trade-offs | Silicon carbide and gallium nitride remain application-specific | Medium |
| Quantum and optical computing | Promising technologies still face major scaling challenges | Commercial applications remain concentrated in specialized areas | Long-term |
If we had to identify one fundamental technical problem, it would be energy-efficient data movement. Moving information between processors, memory, and connected chips increasingly limits how much useful computing performance a system can deliver.
If we focus on the biggest immediate commercial problem, high-bandwidth memory and advanced packaging deserve particular attention. They are already affecting AI accelerator costs, manufacturing plans, and hardware configurations.
And if the question concerns the biggest systemic risk, semiconductor supply-chain concentration remains difficult to ignore. A handful of manufacturers control capabilities that much of the technology industry depends on.
The semiconductor industry's future will depend on whether these bottlenecks improve together. Making transistors smaller is still valuable, but increasingly, the companies that win will be those able to deliver the most useful computing performance per dollar and per watt, reliably and at scale.
If you want more recent data on this point, please see our latest semiconductor industry report.
Our methodology
This analysis identifies the semiconductor industry's biggest unresolved problems using evidence available as of October 28, 2026. We examined manufacturing economics, transistor scaling, memory bandwidth, interconnects, advanced packaging, energy consumption, environmental sustainability, supply-chain concentration, and emerging computing technologies.
We assessed each problem according to three factors: its technical severity, its commercial consequences, and the maturity of available solutions. This allowed us to distinguish immediate manufacturing bottlenecks from structural industry risks and longer-term research challenges. The final severity ranking is our editorial assessment, rather than a numerical score derived from a single dataset.
For market conditions and manufacturing investment, we used the Semiconductor Industry Association's 2025 sales figures and SEMI's semiconductor equipment and capacity forecasts. We compared these industry-wide projections with manufacturers' actual financial results, particularly TSMC's third-quarter 2026 disclosures, to understand how advanced manufacturing is scaling.
For technical constraints, we examined TSMC's 2-nanometer and A16 manufacturing roadmaps, Intel's 18A process technology, ASML's lithography developments, imec's interconnect research, and the UCIe Consortium's chiplet specifications. We distinguished experimental research results from technologies already deployed in commercial production.
We examined memory constraints using TrendForce's September 2026 HBM outlook, including its 2027 pricing forecast and the manufacturing trade-offs between different memory-stack configurations. These forecasts describe expected market conditions rather than guaranteed outcomes.
For electricity and cooling, we used the International Energy Agency's 2026 energy and AI assessment. We considered both the efficiency of individual computing systems and the infrastructure required to deploy them. For environmental impacts, we compared TSMC's total water usage with its unit-efficiency figures to avoid confusing improvements in manufacturing intensity with reductions in absolute consumption.
We also considered geographical concentration, mature-node capacity, and workforce requirements. The US workforce estimate comes from the Semiconductor Industry Association and Oxford Economics' 2023 study and is treated as a conditional forecast for 2030, not as a measured shortage in 2026.
We prioritized original company disclosures, technical research, industry association reports, and authoritative energy statistics. Where detailed production yields or chip-level economics were unavailable, we avoided inferring them from revenue growth or capacity announcements.
Key sources used for this analysis include: Semiconductor Industry Association on 2025 global chip sales, SEMI's 300mm manufacturing equipment outlook, TSMC's third-quarter 2026 management report, TSMC's 2nm technology overview, Intel Foundry's 18A technology documentation, TSMC's A16 technology overview, ASML's 2025 annual report, and imec's CFET device research.
Additional sources include: TrendForce's September 2026 HBM outlook, TSMC's advanced packaging documentation, UCIe Consortium specifications, SEMI's semiconductor equipment market intelligence, International Energy Agency's 2026 Energy and AI assessment, IEA's supporting energy datasets, TSMC's 2025 annual report, SIA and Oxford Economics' semiconductor workforce study, SEMI's 200mm fab outlook, and SIA's State of the US Semiconductor Industry report.
Our report covering the semiconductor market gets updated several times a month, so you always get the latest view of where things stand.
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